The present invention relates to a scrambled video signal processor.
In a CATV system, a video signal of a "pay" channel is scrambled. The scrambled signal is unscrambled (decoded) only by subscribers who contracted to receive the "pay" channel.
The signal of a typical conventional video scrambling system of this type is illustrated in FIG. 1. Scrambling is performed after a video signal is inverted or a synchronous signal is offset, and the resultant scrambled video signal is transmitted. Reference symbol T1 in FIG. 1 denotes an inversion period of the video signal; and T2 and T3, offset periods of the synchronous signal.
In order to descramble the scrambled signal, the inversion position of the video signal or the offset position of the synchronous signal must be detected. Such position data is inserted in a vertical blanking period and is transmitted from an encoder.
FIG. 2 is a general block diagram of a system for descrambling the scrambled signal. A video signal is supplied to pedestal clamp circuit 12, data sampling circuit 15, and synchronous signal separation circuit 16 through input terminal 11. Control circuit 17 generates a data sampling timing signal on the basis of the input synchronous signal separated by separation circuit 16. This timing signal is supplied to sampling circuit 15. Sampling circuit 15 receives the data sampling timing signal, extracts various types of position data from the data sampling timing signal to control circuit 17. Control circuit 17 supplies timing signals to pedestal control circuit 18 and video signal inverter 13 on the basis of input position data. Pedestal control circuit 18 supplies a control signal to clamp circuit 12 during the pedestal period to correct the pedestal level in response to the timing signal from circuit 17. More specifically, pedestal control circuit 18 receives feedback data from video output terminal 14, determines whether the detected pedestal level is set at a desired level, and generates the control signal corresponding to the discrimination result. Circuit 18 also supplies a reference voltage to video signal inverter 13. Inverter 13 inverts (descrambles) the input video signal in the positive or negative direction with respect to the reference voltage. An inverted signal appears at output terminal 14. As shown in FIG. 1, the inversion reference of the video signal or the offset position of the synchronous signal is predetermined. As shown in FIG. 1, if a maximum amplitude level of the video signal is defined as 100 IRE, an inversion reference voltage level is 50 IRE, and a pedestal offset level is 90 IRE.
As described above, the video signal is inverted at a given level, and the pedestal level of the synchronous signal is offset, thus descrambling the video signal. The CATV system described above uses a feed back system without good follow-up characteristics. Therefore, if disturbance acts on pedestal control circuit 18 to store erroneous data therein, it takes a long period of time to stabilize the system. Control circuit 18 samples a voltage during the pedestal period to store level data in a capacitor. The stored level data is used as a control signal. If noise is mixed in during the pedestal period, an inaccurate DC level voltage is stored in the capacitor. If pedestal clamping is performed using the error data, the resultant video signal has an inaccurate DC descrambling level. As a result, the display image becomes not clear, and the occurrence of line flicker remains for a long time because a feedback system, whose response speed is generally low, is adapted to effect the descrambling.